With the continually increasing demand for smaller circuit structures and faster device performance, copper line resistivity has continued to climb, degrading the interconnect performance of the nodes. Beyond 7 nm nodes, the increased resistivity of the lines in the nodes requires the use of more and more asymmetric line/space (L/S), with a wider line than the space. However, directly printing asymmetric line/space with wider line critical dimension (CD) has proven problematic. For instance, the pitch required for 7 nm nodes is in the range of 36 to 48 nanometers (nm), while for 5 nm it is 26-32 nm, and for 3 nm the required pitch could be below 24 nm. Conventional self-aligned via (SAV) patterning techniques become a challenge at approximately 48 nm, even for symmetric L/S, and thus directly printing wide line L/S requires integration scheme changes. Additionally, conventional pillar blocks can be used to print down to approximately 30 nm if printing symmetric L/S, but asymmetric L/S below 30 nm would likely require alternative integration techniques, making printing and cutting asymmetric L/S difficult at such small sizes.
A significant problem with direct printing asymmetric L/S is the block placement for patterning. In a conventional Self Aligned Double Patterning (SADP) integration scheme, the block must land on two spacers. Thus, the block placement error margin is very low. With symmetric L/S, the edge placement error is roughly one quarter of the pitch (e.g. 7 nm for 28 nm pitch). In an asymmetric L/S with wider spacer, rather than wider line, the block placement error tolerance is relaxed, as the spacers have widened. However, as the spacer narrows and the line widens, the margin for error quickly decreases, as landing a block on two very narrow spacers requires a high level of accuracy which is not currently possible.
Previous asymmetric L/S nodes utilized patterning of symmetric L/S nodes, and relied upon the deposition of a barrier material via physical vapor deposition (PVD) to widen the line as the barrier was deposited prior to Cu fill. However, again, as the size of the lines get smaller and the pitch get smaller, PVD becomes ineffective for applying a barrier layer in the lines. Instead, chemical vapor deposition (CVD) or atomic layer deposition (ALD) are required for applying a barrier layer. Neither CVD nor ALD widen the trench upon deposition as PVD does. Therefore, widening the line to create an asymmetric L/S for the sub-7 nm nodes is not possible with previous techniques.
It is desirable to develop methods of widening the lines in nodes of such a small pitch without requiring direct printing of an asymmetric L/S.